RISC-V processor design

Abacus Semiconductor develops a patented Heterogeneous Accelerated Compute (HAC) architecture, also called Kloth Architecture, based on adding a scale-out port onto each CPU and accelerator core with unified interfaces between processors, accelerators and smart multi-homed memories. The company has developed processors, accelerators and smart multi-homed memories targeting AI, HPC, cloud and database workloads, with first silicon prototypes in development, dev kits for research institutions, and OEM partnerships underway.

accelerator designhardware support for virtualization and securitymemory subsystem designsilicon prototypingVerilog re-implementation of RISC-V

ArrayFold builds radiation-tolerant processors, AI accelerators, and evaluation hardware for CubeSats and small satellites. Founded in 2025 by Trevor Peyton, it is a privately held, certified veteran-owned small business based in Indiana. Its chips include AF-X1 (in development), AF-X2 (in design), AF-A1 (in characterization), and AF-R1 (silicon validated).

AI accelerator designECC memoryFD-SOI processIP licensingmemory scrubbingradiation-tolerant chip designtriple modular redundancy

Codasip is a pioneer of CHERI technology and the first to offer a commercial CHERI RISC-V 64-bit application core. The company provides high-performing, silicon-proven RISC-V processor IP, including high-performance embedded cores, application cores, and automotive cores, along with Codasip Studio and CodAL architecture description language for customizable processor design.

architecture licensingCHERI memory protectioncustom instruction extensionfunctional safety (ASIL-D certified processors)processor customization